<!DOCTYPE html>

<html>
<head>
<meta charset="UTF-8">
<link href="style.css" type="text/css" rel="stylesheet">
<title>COMISD—Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS </title></head>
<body>
<h1>COMISD—Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op /En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>66 0F 2F /r COMISD xmm1, xmm2/m64</td>
<td>RM</td>
<td>V/V</td>
<td>SSE2</td>
<td>Compare low double-precision floating-point values in xmm1 and xmm2/mem64 and set the EFLAGS flags accordingly.</td></tr>
<tr>
<td>VEX.128.66.0F.WIG 2F /r VCOMISD xmm1, xmm2/m64</td>
<td>RM</td>
<td>V/V</td>
<td>AVX</td>
<td>Compare low double-precision floating-point values in xmm1 and xmm2/mem64 and set the EFLAGS flags accordingly.</td></tr>
<tr>
<td>EVEX.LIG.66.0F.W1 2F /r VCOMISD xmm1, xmm2/m64{sae}</td>
<td>T1S</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Compare low double-precision floating-point values in xmm1 and xmm2/mem64 and set the EFLAGS flags accordingly.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>T1S</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr></table>
<h2>Description</h2>
<p>Compares the double-precision floating-point values in the low quadwords of operand 1 (first operand) and operand 2 (second operand), and sets the ZF, PF, and CF flags in the EFLAGS register according to the result (unor-dered, greater than, less than, or equal). The OF, SF and AF flags in the EFLAGS register are set to 0. The unor-dered result is returned if either source operand is a NaN (QNaN or SNaN).</p>
<p>Operand 1 is an XMM register; operand 2 can be an XMM register or a 64 bit memory</p>
<p>location. The COMISD instruction differs from the UCOMISD instruction in that it signals a SIMD floating-point invalid operation exception (#I) when a source operand is either a QNaN or SNaN. The UCOMISD instruction signals an invalid numeric exception only if a source operand is an SNaN.</p>
<p>The EFLAGS register is not updated if an unmasked SIMD floating-point exception is generated.</p>
<p>VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.</p>
<p>Software should ensure VCOMISD is encoded with VEX.L=0. Encoding VCOMISD with VEX.L=1 may encounter unpredictable behavior across different processor generations.</p>
<h2>Operation</h2>
<p><strong>COMISD (all versions)</strong></p>
<pre>RESULT (cid:197)(cid:3)OrderedCompare(DEST[63:0] &lt;&gt; SRC[63:0]) {
(* Set EFLAGS *) CASE (RESULT) OF
    UNORDERED: ZF,PF,CF (cid:197) 111;
    GREATER_THAN: ZF,PF,CF (cid:197) 000;
    LESS_THAN: ZF,PF,CF (cid:197) 001;
    EQUAL: ZF,PF,CF (cid:197) 100;
ESAC;
OF, AF, SF (cid:197)0; }</pre>
<h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
<p>VCOMISD int _mm_comi_round_sd(__m128d a, __m128d b, int imm, int sae);</p>
<p>VCOMISD int _mm_comieq_sd (__m128d a, __m128d b)</p>
<p>VCOMISD int _mm_comilt_sd (__m128d a, __m128d b)</p>
<p>VCOMISD int _mm_comile_sd (__m128d a, __m128d b)</p>
<p>VCOMISD int _mm_comigt_sd (__m128d a, __m128d b)</p>
<p>VCOMISD int _mm_comige_sd (__m128d a, __m128d b)</p>
<p>VCOMISD int _mm_comineq_sd (__m128d a, __m128d b)</p>
<h2>SIMD Floating-Point Exceptions</h2>
<p>Invalid (if SNaN or QNaN operands), Denormal.</p>
<h2>Other Exceptions</h2>
<table class="exception-table">
<tr>
<td>VEX-encoded instructions, see Exceptions Type 3;</td></tr>
<tr>
<td>EVEX-encoded instructions, see Exceptions Type E3NF.</td></tr>
<tr>
<td>If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.</td></tr></table></body></html>